Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/109131
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Type: Journal article
Title: Optimal memory size formula for moving-average digital phase-locked loop
Author: Ahn, C.
Shi, P.
Hyun You, S.
Citation: IEEE Signal Processing Letters, 2016; 23(12):1844-1847
Publisher: IEEE
Issue Date: 2016
ISSN: 1070-9908
1558-2361
Statement of
Responsibility: 
Choon Ki Ahn, Peng Shi, Sung Hyun You
Abstract: This letter proposes a new moving-average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs.
Keywords: Digital phase-locked loop (DPLL); moving average; optimal memory size; robustness; unbiasedness
Rights: © 2016 IEEE.
RMID: 0030074911
DOI: 10.1109/LSP.2016.2623520
Grant ID: http://purl.org/au-research/grants/arc/DP140102180
Appears in Collections:Electrical and Electronic Engineering publications

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