Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/118094
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dc.contributor.authorKalbasi, M.-
dc.contributor.authorNikmehr, H.-
dc.date.issued2019-
dc.identifier.citationIEEE Transactions on Circuits and Systems, Part 2: Express Briefs, 2019; 66(1):146-150-
dc.identifier.issn1549-7747-
dc.identifier.issn1558-3791-
dc.identifier.urihttp://hdl.handle.net/2440/118094-
dc.description.abstract2-D convolution has been used as a subsystem for filtering and enhancement in a wide range of signal and image processing applications. It is not only a memory intensive operation but also a compute intensive process. The previous efforts to improve the performance of 2-D convolution have primarily focused on the memory access challenges. However, the convolver's performance is highly dependent on the efficient design of the computation units, which can be enhanced significantly by employing some techniques such as pipelining. In this brief, a pipelined with low pixel access rate architecture for implementation of 2-D convolution is presented. Compared to the conventional convolvers, the proposed design involves a fixed (independent to the problem/kernel) size, and a significantly shorter critical path specifically for large kernel sizes where the proposed convolver works with 283-MHz clock frequency, on a Xilinx Virtex-7 (XC7V2000t) field-programmable gate array, for a 3 × 3 kernel. Additionally, the required pixel access rate of the new scheme is less than that of the state-of-the-art methods, which is only 849 Mb/s for a 3 × 3 kernel and 8-bit pixels. The improvements in the critical path delay and the required pixel access rate are obtained without significant increase in the resource utilization.-
dc.description.statementofresponsibilityMahdi Kalbasi, Hooman Nikmehr-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.rights© 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.-
dc.source.urihttp://dx.doi.org/10.1109/tcsii.2018.2832064-
dc.subject2-D convolution; pipelining; real-time image processing; large kernel size-
dc.titleA fine-grained pipelined 2-D convolver for high-performance applications-
dc.typeJournal article-
dc.identifier.doi10.1109/TCSII.2018.2832064-
pubs.publication-statusPublished-
Appears in Collections:Aurora harvest 8
Electrical and Electronic Engineering publications

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