A low power, high speed threshold logic and its application to the design of novel carry lookahead adders

Abstract

The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.