Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/28404
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Type: Conference paper
Title: Low power serial-parallel bootstrapped dynamic shift register
Author: Lee, L.
Al-Sarawi, S.
Abbott, D.
Citation: Smart structures, devices, and systems : 16-18 December 2002, Melbourne, Australia / Erol C. Harvey, Derek Abbott, Vijay K. Varadan (eds.), pp. 188-196
Publisher: SPIE
Publisher Place: CDROM
Issue Date: 2002
Series/Report no.: Proceedings of SPIE--the International Society for Optical Engineering ; 4935.
ISBN: 0-8194-4730-7
ISSN: 0277-786X
1996-756X
Conference Name: International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia)
Editor: Harvey, E.C.
Abbott, D.
Varadan, V.K.
Statement of
Responsibility: 
Leo Lee, Said F. Al-Sarawi, and Derek Abbott
Abstract: In this paper a new low power area efficient serial-to-parallel shift register design is presented. The design of the register only contains 4 transistors per stage and uses a capacitive bootstrapping technique to offset the threshold voltage drop of MOSFETs. We shall refer to this logic family as Non-Ratioed Bootstrap Logic (NRBL). The intended target applications are in smart sensor arrays and image sensors for use in the select registers to control the photo diode array.
Description: © 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
DOI: 10.1117/12.472851
Published version: http://dx.doi.org/10.1117/12.472851
Appears in Collections:Aurora harvest 2
Electrical and Electronic Engineering publications

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