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|Title:||Low power serial-parallel bootstrapped dynamic shift register|
|Citation:||Smart structures, devices, and systems : 16-18 December 2002, Melbourne, Australia / Erol C. Harvey, Derek Abbott, Vijay K. Varadan (eds.), pp. 188-196|
|Series/Report no.:||Proceedings of SPIE--the International Society for Optical Engineering ; 4935.|
|Conference Name:||International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia)|
|Leo Lee, Said F. Al-Sarawi, and Derek Abbott|
|Abstract:||In this paper a new low power area efficient serial-to-parallel shift register design is presented. The design of the register only contains 4 transistors per stage and uses a capacitive bootstrapping technique to offset the threshold voltage drop of MOSFETs. We shall refer to this logic family as Non-Ratioed Bootstrap Logic (NRBL). The intended target applications are in smart sensor arrays and image sensors for use in the select registers to control the photo diode array.|
|Description:||© 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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