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https://hdl.handle.net/2440/28408
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Type: | Conference paper |
Title: | Threshold logic parallel counters for 32-bit multipliers |
Author: | Celinski, P. Cotofana, S. Abbott, D. |
Citation: | Smart structures, devices, and systems : 16-18 December 2002, Melbourne, Australia / Erol C. Harvey, Derek Abbott, Vijay K. Varadan (eds.), pp. 205-214 |
Publisher: | SPIE |
Publisher Place: | CDROM |
Issue Date: | 2002 |
Series/Report no.: | Proceedings of SPIE--the International Society for Optical Engineering ; 4935 |
ISBN: | 0-8194-4730-7 |
ISSN: | 0277-786X 1996-756X |
Conference Name: | International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia) |
Editor: | Harvey, E.C. Abbott, D. Varadan, V.K. |
Statement of Responsibility: | Peter Celinski, Sorin D. Cotofana, and Derek Abbott |
Abstract: | In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits. |
Description: | © 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only. |
DOI: | 10.1117/12.477382 |
Published version: | http://dx.doi.org/10.1117/12.477382 |
Appears in Collections: | Aurora harvest 2 Electrical and Electronic Engineering publications |
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