Embedding meshes and tori on double-loop networks of the same size

Abstract

Double-loop networks are extensions of ring networks and are widely used in the design and implementation of local area networks and parallel processing architectures. However, embedding of other types of networks on double-loop networks has not been well studied due to the topological complexity of double-loop networks. The traditional L-shape, designed to compute the diameter of double-loop networks, is not effective to solve the embedding problem. We propose a novel tessellation approach to partition the geometric plane of double-loop networks into a set of parallelogram tiles, called P-shape. Based on the characteristics of P-shape, we design a simple embedding scheme, namely, P-shape embedding, that embeds meshes and tori on double-loop networks in a systematic way. Under P-shape embedding, we evaluate the embedding metrics of dilation, average dilation, and congestion, which depend heavily on the parameters of P-shape. A main merit of P-shape embedding is that a large fraction of embedded mesh/torus edges have edge dilation 1, resulting in a low average dilation. These are the first results, to our knowledge, for embedding meshes and tori on double-loop networks which is of great significance due to the popularity of these architectures. Our P-shape construction bridges between regular graphs and double-loop networks, and provides a powerful tool for studying double-loop networks.